1. Field of the Invention
The present invention relates to a computer system mounted on, e.g. an LSI (Large Scale Integration) circuit and using DMA (Direct Memory Access) transfer.
2. Description of the Background Art
A computer system with a DMA controller mounted thereon is conventional. In the event of data transfer, e.g. when data received from an external unit are written in to a main storage, or data stored in the main storage are read out and output to the external unit, a computer system of the type operable at a lower operational speed is designed to give a bus access right to a CPU (Central Processing Unit) so as to cause data to be transferred between the CPU and the main storage. By contrast, a computer system of the type operable at a higher operational speed is adapted to give a bus access right to the DMA controller because data transfer via the CPU is time-consuming. This type of computer system causes the DMA controller to control an I/O (Input/Output) module or interface connected to an external unit such that data transfer to and from the main storage is directly effected without the intermediary of the CPU to thereby implement DMA control.
A specific prior art computer system with a DMA controller mounted thereon will be described with reference to FIG. 7. As shown, the computer system, generally 700, includes a main storage 704 for storing program sequences and data under the control of a CPU 702. The main storage 704 is connected to the CPU 702 and an I/O module 708 via a bus 706 in order to effect data transfer. A DMA controller 712 is used to implement direct data transfer between the I/O module 708 and the main storage 704 without the intermediary of the CPU 702. At this instant, a bus arbitrator 714 arbitrates the CPU 702 and the DMA controller 712 as to the right to use the bus 706.
The I/O module 708 plays the role of an interface that connects the external unit 710 to the computer system 700 for implementing the transfer of received data and data to be transmitted (referred to as transmission data hereinafter) and includes a buffer memory 716 for temporarily storing such data.
In the event of transfer of received data to the main storage 704, the computer system 700 would, if designed operable at a low operational speed, write in the received data to the main storage 704 via the CPU 702. By contrast, the computer system 700 would, if designed operable at a high operational speed, use the DMA controller 712 to directly transfer data to the main storage 704 over the bus 706 because data transfer using the CPU 702 is time-consuming.
The bus arbitrator 714 switches a bus access right every bus access cycle, which is a single period for giving the bus access right, in response to a bus access right request signal. The bus arbitrator 714 therefore does not have to switch the bus access right when the bus access right request signal is not input thereto.
Reference will be made to FIG. 8 for describing how received data are transferred from the external unit 710 to the main storage 704 in the conventional computer system 700. As shown, received data are fed from the external unit 710 to the I/O module 708 (step 802). In response, the I/O module 708 generates a request signal for requesting the transfer of the received data and delivers the request signal to the DMA controller 712 (step 804).
On receiving the request signal, the DMA controller 712 generates a bus access right request signal requesting the use of the bus 706 and delivers the request signal to the bus arbitrator 714 (step 806). Assume that the bus arbitrator 714 has given the bus access right to the CPU 702 when having received the bus access right request signal. Then, the bus arbitrator 714 waits until the break of the above bus access cycle, and then releases the bus access right given to the CPU 702 (step 808).
Subsequently, the bus arbitrator 714 generates a response signal representative of the release of the bus access right, and feeds it to the DMA controller 712 such that the bus access right is given to the DMA controller 712 (step 810). Upon the receipt of the response signal, the DMA controller 712 executes the bus access right and transfers received data from the I/O module 708 to the main storage 704, i.e. executes DMA transfer (step 812).
After the DMA transfer stated above, the DMA controller 712 generate a release signal indicative of the release of the bus access right and feeds the release signal to the bus arbitrator 714. In response, the bus arbitrator 714 releases the bus access right given to the DMA controller 712 and again gives the bus access right to the CPU 702 (step 814).
On the other hand, when the transfer of received data from the I/O module 708 ends, the I/O module 708 feeds a report indicative of the end of data transfer to the CPU 702 by interrupt (step 816). This allows the CPU 702 to, e.g. read out received data from the main storage 704.
As state above, the computer system 700 is capable of directly transferring, with the DMA controller 712, data transferred from the I/O module 708 to the main storage 704 without the intermediary of the CPU 702, and capable of arbitrating, with the bus arbitrator 714, the CPU 702 and the DMA 712 as to the bus access right.
U.S. Pat. No. 5,307,468 to Schlage discloses a data processing system including a main memory and a CPU directly connected to each other, a first switching device for controlling connection between the CPU and the main memory, and a second switching device for controlling connection between a system bus and the main memory. The first and second switching devices are interconnected such that only one of them can release connection between the CPU or the system bus and the main memory, thereby improving the performance of the data processing system. This allows the data processing system to concurrently process as many tasks as possible for thereby reducing the waiting time of the system bus. Further, the CPU and I/O unit, connected to the system bus in a conventional method, can simultaneously access the main memory via a DAM unit.
The computer system 700 with the DMA controller shown in FIG. 7 of the accompanying drawings of the present patent application has some problems left unsolved, as will be described hereinafter. Although the I/O module 708 is connected to the main storage 704 via the bus 706, an access to the main storage 704 is not practicable without the arbitration of a bus access right including a plurality of steps, i.e. a bus access right release request, data transfer, bus access right release and so forth, increasing a period of time necessary for data transfer.
In the computer system 700, the I/O module 708 transfers even a great amount of data to the main storage 704 in a single bus access cycle, occupying thus the bus 706 over several-ten consecutive data transfer cycles. Consequently, the CPU 702, for example, cannot access not only the main storage 704 but also other circuits, or peripherals, over such data transfer cycles. This problem is more serious when a plurality of I/O modules 708 are included in the computer system 700 and request to access the main storage 704 at the same time because the bus access right is sequentially given to the I/O modules 708 for data transfer so as to perform data transfer for each of the I/O modules 708, thus occupying the main storage 704 for a much longer period of time.
While the bus 706 included in the computer system 700 is usually implemented as a synchronous bus, data transfer is effected by a protocol synchronous to a clock signal. As a result, overheads such as a synchronization loss for one or more clock signal period occur in the event of data output to or input from the bus 706.
Moreover, the I/O module 708, which is required to transfer data at a higher transfer rate, includes the buffer memory 716 for temporarily storing received data or data for transmission. However, when the computer system 700 is implemented in, e.g. an LSI form, wider strips of power supply wiring and a number of bus connections must be arranged around the buffer memory 716 because of the layout of the LSI elements. Consequently, despite that the buffer memory 716 is smaller in size than the main storage 704, the former is apt to become two times or more greater in size than the latter when the spaces for the power supply wiring and bus connections are taken into account.